Define, document and communicate RAS and Error Handling requirements to components/ subsystems, and review implementations for correctness and completeness.
Assess and identify error mitigations to address the needs of a wide range of market segments.
Participate in new product development, comprehend customer technical requirements, develop architectural solutions to meet those requirements
Author specifications and other technical collateral
Work with design and verification teams to ensure implementation is in accordance with the specification
Minimum Requirements: Bachelor's + 6 years or a Master's +4 years or PhD + 2 year of relevant work experience in datacenter or server CPU architecture and logic design and validation. Focus area should include RAS architecture and interaction with operating system software and platform firmware in a datacenter. Preferred Qualifications: Knowledge of modern architectural techniques regarding reliability of microprocessors. 6+ years of experience in architecture/logic design, including 3+ years of experience in processor RAS features, error handling, detection, and recovery In-depth understanding of the interaction of machine check architecture and error flows with system firmware/software. Detailed knowledge of multiprocessor system architecture, memory and input- output subsystems, high-speed interconnects, operating systems/hypervisors, platform firmware, Error correcting codes (ECC). Experience in RTL development design environments Experience successfully interacting with cross-disciplinary teams, tracking deliverables and milestones, with attention to detail. Strong debug experience.
Corporate / senior
Santa Clarita , United States