Behavioral Modeling with VHDL-AMS

Cadence Design Systems
Posted on

Type

Other

Length : 3 days

Course Description

This advanced Engineer Explorer course provides an in-depth approach to behavioral modeling of analog and mixed-signal design blocks and systems. Students are required to have a working knowledge of the Virtuoso® AMS Designer simulator or to complete the course prerequisite of taking the Virtuoso AMS Designer course.

In this three-day course, you will learn how to create parameterized VHDL-AMS models for analog/mixed-signal blocks and verify their functionality and performance using the Virtuoso AMS Designer simulator.

Learning Objectives

In this course you will:

Understand when and how to use behavioral modeling.

Learn how to create VHDL-AMS for analog, mixed-signal, and multi-disciplinary designs.

Verify the functionality and performance of the models you create using the Virtuoso® AMS Designer simulator.

Learn how to troubleshoot your models for optimum performance.

Progressively, generate your own package of useful utilities for handling discontinuities, etc. for the sake of re-use.

Understand how to benefit the most from multi-language support in Virtuoso® AMS Designer simulator.

Understand Virtuoso® AMS Designer new features specific for VHDL-AMS

Through real-life examples, see how to effectively deploy the models you have created in your design flow. Examples of mixed-signal models created are:

Alarm clock,

Multiplexer,

Projectile,

Differential Amplifiers,

PLL blocks,

AM-system,

FM-system,

RS232 tx driver,

Modelling Jitter,

Switched-mode power supply,

ADC model,

Adding Noise to the ADC model

Thermal resistance

Heatsink model,

Capacitive Accelerometer MEM system.

Creating the analog_pkg package,

and more

Audience

Analog/Mixed-Signal IC Designers

Library Developers

CAD Engineers

Modeling Engineers

Software

Virtuoso® AMS Designer Environment

Virtuoso® AMS Designer Simulator

Prerequisites

You must have completed the Virtuoso® AMS Designer course before taking this class.

Being familiar with any HDL language, specifically, VHDL, Verilog, Verilog-A, or Verilog-AMS would help you gain the maximum benefit from taking this advanced Engineer Explorer course.

Course Agenda

Day 1

What is Behavioral Modeling

Starting with VHDL-AMS

Modeling Digital Blocks

Modeling Analog Blocks

Day 2

Mixed-Signal Technology

Practical Aspects of Analog Behavioral Models

Practical Aspects of Mixed-signal Behavioral Models

Advanced Language Constructs

Multidisciplinary Modeling

Day 3

Virtuoso® AMS Designer VHDL-AMS support

Virtuoso® AMS Designer Simulation Architecture

Virtuoso® AMS Designer Use Models

Verilog-AMS versus VHDL-AMS

Integrating your models in real-life

Special Notes

This is an advanced course. You are expected to run the Virtuoso AMS Designer software without assistance to solve loosely defined problems. Labs will be exploratory rather than step-by-step.

Click here to view course learning maps, and here for complete course catalogs.

More Information

Posted on

Type

Other

Bengaluru%2C%20India

Bengaluru , India